1. Field
Aspects of exemplary embodiments of the present invention relate to a semiconductor device having a buried power rail.
2. Related Art
When forming a device including a plurality of semiconductor devices, such as integrated circuits, standard cells may be used as a base unit for designing and manufacturing the integrated circuits. The standard cell(s) may be used to form one or more functional circuits, and each standard cell may have the same footprint (e.g., may have a standard footprint). Using standard cells when designing complex circuits and components reduces design and manufacture costs.
In use, each standard cell of a device requires power input (Vdd) and ground (Vss) connections. To power the various components thereof, each standard cell is generally coupled to a power rail which is electrically connected to an active layer of the standard cell to provide the power (Vdd). In some instances, a plurality of power rails may be provided for each standard cell to respectively provide the power (Vdd) and the ground (Vss).
Furthermore, to provide the power to each power rail, a chip level power grid is included in the device. The chip level power grid may run through or between the various standard cells and is electrically connected to the power rails at various points along a length of the power rails.
Referring to FIG. 1, a standard cell 1 includes a power rail 10, contacts 30 (e.g., a contact layer), and a Via 20 (e.g., a tap). The Via 20 extends between and electrically connects the power rail 10 to the contacts 30, thereby providing power to the standard cell.
The standard cell 1 further includes an active layer 40 (e.g., fins or a nanosheet), including source/drain terminals (e.g., source/drain electrodes), and gate electrodes 50. While not shown, the active layer 40 is separated from a gate electrode by a gate insulation layer. As can be seen in FIG. 1, the power rail 10 is arranged above the contacts 30 and above the active layer 40.
Generally, a standard cell is designed having a stacked structure of various metal layers, termed M1-Mx, for example. The lowest metal layer is often termed M1 and is the first metal layer above an interconnection layer (e.g., a metal interconnection layer), sometimes termed M0.
The metal layers M1-Mx each include routing tracks, and various interconnections 12, 13 are formed in the routing tracks to connect various components of the standard cell to each other and to other standard cells. Generally, designs including a plurality of standard cells may include up to about eight metal layers M1-M8. However, semiconductor devices can be manufactured with more or fewer metals layers.
In FIG. 1, the power rail 10 of the standard cell 1 is arranged in a first metal layer M1, above the interconnection layer M0, in which the active layer 40 and the gate electrodes 50 are arranged. The interconnection layer M0 may be the first metal layer on a substrate and is electrically insulated from the first metal layer M1 by an insulating layer (e.g., an electrically insulating layer).
Due to the power rail 10 being arranged in a different layer than the active layer 40, the Via 20 is included. The Via 20 extends through the insulating layer between the first metal layer M1 and the interconnection layer M0 and electrically connects the power rail 10 to the contacts 30 and, thus, to the active layer 40.
FIG. 5 is a schematic side view of the standard cell 1 illustrated in FIG. 1. In FIG. 5, the interconnection layer M0 is indicated by 1000 and is where the contacts 30 and the active layer 40 are arranged. The first metal layer M1 is indicated by 1010 and is at which the power rails 10 and routing tracks 90 are arranged. As can be seen, the power rails 10 occupy the same level in the standard cell 1 as the routing tracks 90, thus reducing the space available for the routing tracks 90 in the standard cell 1.
Moreover, because the power rail 10 is included in one of the metal layers M1-Mx, the power rail 10 occupies space that could otherwise be used for routing tracks 90 and various interconnections. In addition, the power rail 10 is connected to the active layer 40 by the Via 20, and an IR drop across the Via 20 must be considered in designing a semiconductor device including the standard cell 1.